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	<id>https://wiki.frotmail.nl/index.php?action=history&amp;feed=atom&amp;title=ESP%3A_linker_files</id>
	<title>ESP: linker files - Revision history</title>
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	<updated>2026-08-06T03:41:10Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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	<entry>
		<id>https://wiki.frotmail.nl/index.php?title=ESP:_linker_files&amp;diff=43&amp;oldid=prev</id>
		<title>Eric: Created page with &quot;In alle online docs en voorbeelden zijn er nogal veel versies van de linker files in omloop. Op deze pagina staan de files waar ik succes mee heb gehad:  =common.ld= pad: /opt/Sming/Sming/compiler/ld/)  /*        common.ld  */        PHDRS  {    dport0_0_phdr PT_LOAD;    dram0_0_phdr PT_LOAD;    dram0_0_bss_phdr PT_LOAD;    iram1_0_phdr PT_LOAD;    irom0_0_phdr PT_LOAD;  }      /*  Default entry point:  */  ENTRY(call_user_start)  EXTERN(_DebugExceptionVector)  EXTERN(_D...&quot;</title>
		<link rel="alternate" type="text/html" href="https://wiki.frotmail.nl/index.php?title=ESP:_linker_files&amp;diff=43&amp;oldid=prev"/>
		<updated>2022-04-05T09:10:54Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;In alle online docs en voorbeelden zijn er nogal veel versies van de linker files in omloop. Op deze pagina staan de files waar ik succes mee heb gehad:  =common.ld= pad: /opt/Sming/Sming/compiler/ld/)  &lt;span class=&quot;autocomment&quot;&gt;common.ld: &lt;/span&gt;        PHDRS  {    dport0_0_phdr PT_LOAD;    dram0_0_phdr PT_LOAD;    dram0_0_bss_phdr PT_LOAD;    iram1_0_phdr PT_LOAD;    irom0_0_phdr PT_LOAD;  }      &lt;span class=&quot;autocomment&quot;&gt;Default entry point:: &lt;/span&gt;  ENTRY(call_user_start)  EXTERN(_DebugExceptionVector)  EXTERN(_D...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;In alle online docs en voorbeelden zijn er nogal veel versies van de linker files in omloop. Op deze pagina staan de files waar ik succes mee heb gehad:&lt;br /&gt;
&lt;br /&gt;
=common.ld=&lt;br /&gt;
pad: /opt/Sming/Sming/compiler/ld/)&lt;br /&gt;
 /*  &lt;br /&gt;
     common.ld&lt;br /&gt;
 */    &lt;br /&gt;
 &lt;br /&gt;
 PHDRS&lt;br /&gt;
 {&lt;br /&gt;
   dport0_0_phdr PT_LOAD;&lt;br /&gt;
   dram0_0_phdr PT_LOAD;&lt;br /&gt;
   dram0_0_bss_phdr PT_LOAD;&lt;br /&gt;
   iram1_0_phdr PT_LOAD;&lt;br /&gt;
   irom0_0_phdr PT_LOAD;&lt;br /&gt;
 }&lt;br /&gt;
 &lt;br /&gt;
 &lt;br /&gt;
 /*  Default entry point:  */&lt;br /&gt;
 ENTRY(call_user_start)&lt;br /&gt;
 EXTERN(_DebugExceptionVector)&lt;br /&gt;
 EXTERN(_DoubleExceptionVector)&lt;br /&gt;
 EXTERN(_KernelExceptionVector)&lt;br /&gt;
 EXTERN(_NMIExceptionVector)&lt;br /&gt;
 EXTERN(_UserExceptionVector)&lt;br /&gt;
 PROVIDE(_memmap_vecbase_reset = 0x40000000);&lt;br /&gt;
 /* Various memory-map dependent cache attribute settings: */&lt;br /&gt;
 _memmap_cacheattr_wb_base = 0x00000110;&lt;br /&gt;
 _memmap_cacheattr_wt_base = 0x00000110;&lt;br /&gt;
 _memmap_cacheattr_bp_base = 0x00000220;&lt;br /&gt;
 _memmap_cacheattr_unused_mask = 0xFFFFF00F;&lt;br /&gt;
 _memmap_cacheattr_wb_trapnull = 0x2222211F;&lt;br /&gt;
 _memmap_cacheattr_wba_trapnull = 0x2222211F;&lt;br /&gt;
 _memmap_cacheattr_wbna_trapnull = 0x2222211F;&lt;br /&gt;
 _memmap_cacheattr_wt_trapnull = 0x2222211F;&lt;br /&gt;
 _memmap_cacheattr_bp_trapnull = 0x2222222F;&lt;br /&gt;
 _memmap_cacheattr_wb_strict = 0xFFFFF11F;&lt;br /&gt;
 _memmap_cacheattr_wt_strict = 0xFFFFF11F;&lt;br /&gt;
 _memmap_cacheattr_bp_strict = 0xFFFFF22F;&lt;br /&gt;
 _memmap_cacheattr_wb_allvalid = 0x22222112;&lt;br /&gt;
 _memmap_cacheattr_wt_allvalid = 0x22222112;&lt;br /&gt;
 _memmap_cacheattr_bp_allvalid = 0x22222222;&lt;br /&gt;
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);&lt;br /&gt;
 &lt;br /&gt;
 SECTIONS&lt;br /&gt;
 {&lt;br /&gt;
 &lt;br /&gt;
   .dport0.rodata : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _dport0_rodata_start = ABSOLUTE(.);&lt;br /&gt;
     *(.dport0.rodata)&lt;br /&gt;
     *(.dport.rodata)&lt;br /&gt;
     _dport0_rodata_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;dport0_0_seg :dport0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .dport0.literal : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _dport0_literal_start = ABSOLUTE(.);&lt;br /&gt;
     *(.dport0.literal)&lt;br /&gt;
     *(.dport.literal)&lt;br /&gt;
     _dport0_literal_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;dport0_0_seg :dport0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .dport0.data : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _dport0_data_start = ABSOLUTE(.);&lt;br /&gt;
     *(.dport0.data)&lt;br /&gt;
     *(.dport.data)&lt;br /&gt;
     _dport0_data_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;dport0_0_seg :dport0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .data : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _data_start = ABSOLUTE(.);&lt;br /&gt;
     *(.data)&lt;br /&gt;
     *(.data.*)&lt;br /&gt;
     *(.gnu.linkonce.d.*)&lt;br /&gt;
     *(.data1)&lt;br /&gt;
     *(.sdata)&lt;br /&gt;
     *(.sdata.*)&lt;br /&gt;
     *(.gnu.linkonce.s.*)&lt;br /&gt;
     *(.sdata2)&lt;br /&gt;
     *(.sdata2.*)&lt;br /&gt;
     *(.gnu.linkonce.s2.*)&lt;br /&gt;
     *(.jcr)&lt;br /&gt;
     _data_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;dram0_0_seg :dram0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .rodata : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _rodata_start = ABSOLUTE(.);&lt;br /&gt;
     *(.sdk.version)&lt;br /&gt;
     *(.rodata)&lt;br /&gt;
     *(.rodata.*)&lt;br /&gt;
     *(.gnu.linkonce.r.*)&lt;br /&gt;
     *(.rodata1)&lt;br /&gt;
     __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);&lt;br /&gt;
     *(.xt_except_table)&lt;br /&gt;
     *(.gcc_except_table)&lt;br /&gt;
     *(.gnu.linkonce.e.*)&lt;br /&gt;
     *(.gnu.version_r)&lt;br /&gt;
     *(.eh_frame)&lt;br /&gt;
     . = (. + 3) &amp;amp; ~ 3;&lt;br /&gt;
     /*  C++ constructor and destructor tables, properly ordered:  */&lt;br /&gt;
 	__dso_handle = ABSOLUTE(.);&lt;br /&gt;
     __init_array_start = ABSOLUTE(.);&lt;br /&gt;
     KEEP (*crtbegin.o(.ctors))&lt;br /&gt;
     KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))&lt;br /&gt;
     KEEP (*(SORT(.ctors.*)))&lt;br /&gt;
     KEEP (*(.ctors))&lt;br /&gt;
     __init_array_end = ABSOLUTE(.);&lt;br /&gt;
     KEEP (*crtbegin.o(.dtors))&lt;br /&gt;
     KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))&lt;br /&gt;
     KEEP (*(SORT(.dtors.*)))&lt;br /&gt;
     KEEP (*(.dtors))&lt;br /&gt;
     /*  C++ exception handlers table:  */&lt;br /&gt;
     __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);&lt;br /&gt;
     *(.xt_except_desc)&lt;br /&gt;
     *(.gnu.linkonce.h.*)&lt;br /&gt;
     __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);&lt;br /&gt;
     *(.xt_except_desc_end)&lt;br /&gt;
     *(.dynamic)&lt;br /&gt;
     *(.gnu.version_d)&lt;br /&gt;
     . = ALIGN(4);		/* this table MUST be 4-byte aligned */&lt;br /&gt;
     _bss_table_start = ABSOLUTE(.);&lt;br /&gt;
     LONG(_bss_start)&lt;br /&gt;
     LONG(_bss_end)&lt;br /&gt;
     _bss_table_end = ABSOLUTE(.);&lt;br /&gt;
     _rodata_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;dram0_0_seg :dram0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .bss ALIGN(8) (NOLOAD) : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     . = ALIGN (8);&lt;br /&gt;
     _bss_start = ABSOLUTE(.);&lt;br /&gt;
     *(.dynsbss)&lt;br /&gt;
     *(.sbss)&lt;br /&gt;
     *(.sbss.*)&lt;br /&gt;
     *(.gnu.linkonce.sb.*)&lt;br /&gt;
     *(.scommon)&lt;br /&gt;
     *(.sbss2)&lt;br /&gt;
     *(.sbss2.*)&lt;br /&gt;
     *(.gnu.linkonce.sb2.*)&lt;br /&gt;
     *(.dynbss)&lt;br /&gt;
     *(.bss)&lt;br /&gt;
     *(.bss.*)&lt;br /&gt;
     *(.gnu.linkonce.b.*)&lt;br /&gt;
     *(COMMON)&lt;br /&gt;
     . = ALIGN (8);&lt;br /&gt;
     _bss_end = ABSOLUTE(.);&lt;br /&gt;
     _heap_start = ABSOLUTE(.);&lt;br /&gt;
 /*    _stack_sentry = ALIGN(0x8); */&lt;br /&gt;
   } &amp;gt;dram0_0_seg :dram0_0_bss_phdr&lt;br /&gt;
 /* __stack = 0x3ffc8000; */&lt;br /&gt;
 &lt;br /&gt;
   .irom0.text : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _irom0_text_start = ABSOLUTE(.);&lt;br /&gt;
     *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.debug.*)&lt;br /&gt;
 	out/build/app_app.a:*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.* .irom.debug.*)&lt;br /&gt;
   *libsming.a:*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.* .irom.debug.*)&lt;br /&gt;
   *libsmingssl.a:*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.* .irom.debug.*)&lt;br /&gt;
     _irom0_text_end = ABSOLUTE(.);&lt;br /&gt;
 	_flash_code_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;irom0_0_seg :irom0_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .text : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _stext = .;&lt;br /&gt;
     _text_start = ABSOLUTE(.);&lt;br /&gt;
      *(.UserEnter.text)&lt;br /&gt;
     . = ALIGN(16);&lt;br /&gt;
     *(.DebugExceptionVector.text)&lt;br /&gt;
     . = ALIGN(16);&lt;br /&gt;
     *(.NMIExceptionVector.text)&lt;br /&gt;
     . = ALIGN(16);&lt;br /&gt;
     *(.KernelExceptionVector.text)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     . = ALIGN(16);&lt;br /&gt;
     *(.UserExceptionVector.text)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     . = ALIGN(16);&lt;br /&gt;
     *(.DoubleExceptionVector.text)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     LONG(0)&lt;br /&gt;
     . = ALIGN (16);&lt;br /&gt;
     *(.entry.text)&lt;br /&gt;
     *(.init.literal)&lt;br /&gt;
     *(.init)&lt;br /&gt;
     *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)&lt;br /&gt;
 	  *(.iram.literal .iram.text.literal .iram.text)&lt;br /&gt;
     *(.fini.literal)&lt;br /&gt;
     *(.fini)&lt;br /&gt;
     *(.gnu.version)&lt;br /&gt;
     _text_end = ABSOLUTE(.);&lt;br /&gt;
     _etext = .;&lt;br /&gt;
   } &amp;gt;iram1_0_seg :iram1_0_phdr&lt;br /&gt;
 &lt;br /&gt;
   .lit4 : ALIGN(4)&lt;br /&gt;
   {&lt;br /&gt;
     _lit4_start = ABSOLUTE(.);&lt;br /&gt;
     *(*.lit4)&lt;br /&gt;
     *(.lit4.*)&lt;br /&gt;
     *(.gnu.linkonce.lit4.*)&lt;br /&gt;
     _lit4_end = ABSOLUTE(.);&lt;br /&gt;
   } &amp;gt;iram1_0_seg :iram1_0_phdr&lt;br /&gt;
 }&lt;br /&gt;
 &lt;br /&gt;
 /* get ROM code address */&lt;br /&gt;
 INCLUDE &amp;quot;../ld/eagle.rom.addr.v6.ld&amp;quot;&lt;br /&gt;
&lt;br /&gt;
=rom0.33.ld=&lt;br /&gt;
In project map, 33 staat hier voor ~33%, een verwijzing naar het feit dat ik hier 33/33/33 probeer te reserveren voor resp. rom0, rom1 en spiffs&lt;br /&gt;
 /* Linker Script for rboot */&lt;br /&gt;
 &lt;br /&gt;
 MEMORY&lt;br /&gt;
 {&lt;br /&gt;
   dport0_0_seg :                        org = 0x3FF00000, len = 0x10&lt;br /&gt;
   dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000&lt;br /&gt;
   iram1_0_seg :                         org = 0x40100000, len = 0x8000&lt;br /&gt;
   irom0_0_seg :                         org = 0x40202010, len = 0x4FF00&lt;br /&gt;
 }&lt;br /&gt;
 &lt;br /&gt;
 INCLUDE &amp;quot;../ld/common.ld&amp;quot;&lt;br /&gt;
&lt;br /&gt;
=rom1.33.ld=&lt;br /&gt;
 /* Linker Script for rboot */&lt;br /&gt;
 &lt;br /&gt;
 MEMORY&lt;br /&gt;
 {&lt;br /&gt;
   dport0_0_seg :                        org = 0x3FF00000, len = 0x10&lt;br /&gt;
   dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000&lt;br /&gt;
   iram1_0_seg :                         org = 0x40100000, len = 0x8000&lt;br /&gt;
   irom0_0_seg :                         org = 0x40262010, len = 0x4FF00&lt;br /&gt;
 }&lt;br /&gt;
 &lt;br /&gt;
 INCLUDE &amp;quot;../ld/common.ld&amp;quot;&lt;br /&gt;
=eagle.rom.addr.v6.ld=&lt;br /&gt;
pad: /opt/esp-open-sdk/xtensa-lx106-elf/xtensa-lx106-elf/sysroot/usr/lib/eagle.rom.addr.v6.ld&lt;br /&gt;
 PROVIDE ( Cache_Read_Disable = 0x400047f0 );&lt;br /&gt;
 PROVIDE ( Cache_Read_Enable = 0x40004678 );&lt;br /&gt;
 PROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );&lt;br /&gt;
 PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );&lt;br /&gt;
 PROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );&lt;br /&gt;
 PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );&lt;br /&gt;
 PROVIDE ( GetUartDevice = 0x40003f4c );&lt;br /&gt;
 PROVIDE ( MD5Final = 0x40009900 );&lt;br /&gt;
 PROVIDE ( MD5Init = 0x40009818 );&lt;br /&gt;
 PROVIDE ( MD5Update = 0x40009834 );&lt;br /&gt;
 PROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );&lt;br /&gt;
 PROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );&lt;br /&gt;
 PROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );&lt;br /&gt;
 PROVIDE ( RcvMsg = 0x40003eac );&lt;br /&gt;
 PROVIDE ( SHA1Final = 0x4000b648 );&lt;br /&gt;
 PROVIDE ( SHA1Init = 0x4000b584 );&lt;br /&gt;
 PROVIDE ( SHA1Transform = 0x4000a364 );&lt;br /&gt;
 PROVIDE ( SHA1Update = 0x4000b5a8 );&lt;br /&gt;
 PROVIDE ( SPI_read_status = 0x400043c8 );&lt;br /&gt;
 PROVIDE ( SPI_write_status = 0x40004400 );&lt;br /&gt;
 PROVIDE ( SPI_write_enable = 0x4000443c );&lt;br /&gt;
 PROVIDE ( Wait_SPI_Idle = 0x4000448c );&lt;br /&gt;
 PROVIDE ( SPIEraseArea = 0x40004b44 );&lt;br /&gt;
 PROVIDE ( SPIEraseBlock = 0x400049b4 );&lt;br /&gt;
 PROVIDE ( SPIEraseChip = 0x40004984 );&lt;br /&gt;
 PROVIDE ( SPIEraseSector = 0x40004a00 );&lt;br /&gt;
 PROVIDE ( SPILock = 0x400048a8 );&lt;br /&gt;
 PROVIDE ( SPIParamCfg = 0x40004c2c );&lt;br /&gt;
 PROVIDE ( SPIRead = 0x40004b1c );&lt;br /&gt;
 PROVIDE ( SPIReadModeCnfig = 0x400048ec );&lt;br /&gt;
 PROVIDE ( SPIUnlock = 0x40004878 );&lt;br /&gt;
 PROVIDE ( SPIWrite = 0x40004a4c );&lt;br /&gt;
 PROVIDE ( SelectSpiFunction = 0x40003f58 );&lt;br /&gt;
 PROVIDE ( SendMsg = 0x40003cf4 );&lt;br /&gt;
 PROVIDE ( UartConnCheck = 0x40003230 );&lt;br /&gt;
 PROVIDE ( UartConnectProc = 0x400037a0 );&lt;br /&gt;
 PROVIDE ( UartDwnLdProc = 0x40003368 );&lt;br /&gt;
 PROVIDE ( UartGetCmdLn = 0x40003ef4 );&lt;br /&gt;
 PROVIDE ( UartRegReadProc = 0x4000381c );&lt;br /&gt;
 PROVIDE ( UartRegWriteProc = 0x400037ac );&lt;br /&gt;
 PROVIDE ( UartRxString = 0x40003c30 );&lt;br /&gt;
 PROVIDE ( Uart_Init = 0x40003a14 );&lt;br /&gt;
 PROVIDE ( _DebugExceptionVector = 0x40000010 );&lt;br /&gt;
 PROVIDE ( _DoubleExceptionVector = 0x40000070 );&lt;br /&gt;
 PROVIDE ( _KernelExceptionVector = 0x40000030 );&lt;br /&gt;
 PROVIDE ( _NMIExceptionVector = 0x40000020 );&lt;br /&gt;
 PROVIDE ( _ResetHandler = 0x400000a4 );&lt;br /&gt;
 PROVIDE ( _ResetVector = 0x40000080 );&lt;br /&gt;
 PROVIDE ( _UserExceptionVector = 0x40000050 );&lt;br /&gt;
 PROVIDE ( __adddf3 = 0x4000c538 );&lt;br /&gt;
 PROVIDE ( __addsf3 = 0x4000c180 );&lt;br /&gt;
 PROVIDE ( __divdf3 = 0x4000cb94 );&lt;br /&gt;
 PROVIDE ( __divdi3 = 0x4000ce60 );&lt;br /&gt;
 PROVIDE ( __divsi3 = 0x4000dc88 );&lt;br /&gt;
 PROVIDE ( __extendsfdf2 = 0x4000cdfc );&lt;br /&gt;
 PROVIDE ( __fixdfsi = 0x4000ccb8 );&lt;br /&gt;
 PROVIDE ( __fixunsdfsi = 0x4000cd00 );&lt;br /&gt;
 PROVIDE ( __fixunssfsi = 0x4000c4c4 );&lt;br /&gt;
 PROVIDE ( __floatsidf = 0x4000e2f0 );&lt;br /&gt;
 PROVIDE ( __floatsisf = 0x4000e2ac );&lt;br /&gt;
 PROVIDE ( __floatunsidf = 0x4000e2e8 );&lt;br /&gt;
 PROVIDE ( __floatunsisf = 0x4000e2a4 );&lt;br /&gt;
 PROVIDE ( __muldf3 = 0x4000c8f0 );&lt;br /&gt;
 PROVIDE ( __muldi3 = 0x40000650 );&lt;br /&gt;
 PROVIDE ( __mulsf3 = 0x4000c3dc );&lt;br /&gt;
 PROVIDE ( __subdf3 = 0x4000c688 );&lt;br /&gt;
 PROVIDE ( __subsf3 = 0x4000c268 );&lt;br /&gt;
 PROVIDE ( __truncdfsf2 = 0x4000cd5c );&lt;br /&gt;
 PROVIDE ( __udivdi3 = 0x4000d310 );&lt;br /&gt;
 PROVIDE ( __udivsi3 = 0x4000e21c );&lt;br /&gt;
 PROVIDE ( __umoddi3 = 0x4000d770 );&lt;br /&gt;
 PROVIDE ( __umodsi3 = 0x4000e268 );&lt;br /&gt;
 PROVIDE ( __umulsidi3 = 0x4000dcf0 );&lt;br /&gt;
 PROVIDE ( _rom_store = 0x4000e388 );&lt;br /&gt;
 PROVIDE ( _rom_store_table = 0x4000e328 );&lt;br /&gt;
 PROVIDE ( _start = 0x4000042c );&lt;br /&gt;
 PROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );&lt;br /&gt;
 PROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );&lt;br /&gt;
 PROVIDE ( _xtos_cause3_handler = 0x40000590 );&lt;br /&gt;
 PROVIDE ( _xtos_ints_off = 0x4000bda4 );&lt;br /&gt;
 PROVIDE ( _xtos_ints_on = 0x4000bd84 );&lt;br /&gt;
 PROVIDE ( _xtos_l1int_handler = 0x4000048c );&lt;br /&gt;
 PROVIDE ( _xtos_p_none = 0x4000dbf8 );&lt;br /&gt;
 PROVIDE ( _xtos_restore_intlevel = 0x4000056c );&lt;br /&gt;
 PROVIDE ( _xtos_return_from_exc = 0x4000dc54 );&lt;br /&gt;
 PROVIDE ( _xtos_set_exception_handler = 0x40000454 );&lt;br /&gt;
 PROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );&lt;br /&gt;
 PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );&lt;br /&gt;
 PROVIDE ( _xtos_set_intlevel = 0x4000dbfc );&lt;br /&gt;
 PROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );&lt;br /&gt;
 PROVIDE ( _xtos_set_vpri = 0x40000574 );&lt;br /&gt;
 PROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );&lt;br /&gt;
 PROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );&lt;br /&gt;
 PROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );&lt;br /&gt;
 PROVIDE ( aes_decrypt = 0x400092d4 );&lt;br /&gt;
 PROVIDE ( aes_decrypt_deinit = 0x400092e4 );&lt;br /&gt;
 PROVIDE ( aes_decrypt_init = 0x40008ea4 );&lt;br /&gt;
 PROVIDE ( aes_unwrap = 0x40009410 );&lt;br /&gt;
 PROVIDE ( base64_decode = 0x40009648 );&lt;br /&gt;
 PROVIDE ( base64_encode = 0x400094fc );&lt;br /&gt;
 PROVIDE ( bzero = 0x4000de84 );&lt;br /&gt;
 PROVIDE ( cmd_parse = 0x40000814 );&lt;br /&gt;
 PROVIDE ( conv_str_decimal = 0x40000b24 );&lt;br /&gt;
 PROVIDE ( conv_str_hex = 0x40000cb8 );&lt;br /&gt;
 PROVIDE ( convert_para_str = 0x40000a60 );&lt;br /&gt;
 PROVIDE ( dtm_get_intr_mask = 0x400026d0 );&lt;br /&gt;
 PROVIDE ( dtm_params_init = 0x4000269c );&lt;br /&gt;
 PROVIDE ( dtm_set_intr_mask = 0x400026c8 );&lt;br /&gt;
 PROVIDE ( dtm_set_params = 0x400026dc );&lt;br /&gt;
 PROVIDE ( eprintf = 0x40001d14 );&lt;br /&gt;
 PROVIDE ( eprintf_init_buf = 0x40001cb8 );&lt;br /&gt;
 PROVIDE ( eprintf_to_host = 0x40001d48 );&lt;br /&gt;
 PROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );&lt;br /&gt;
 PROVIDE ( est_reset_printf_buf_len = 0x4000249c );&lt;br /&gt;
 PROVIDE ( ets_bzero = 0x40002ae8 );&lt;br /&gt;
 PROVIDE ( ets_char2xdigit = 0x40002b74 );&lt;br /&gt;
 PROVIDE ( ets_delay_us = 0x40002ecc );&lt;br /&gt;
 PROVIDE ( ets_enter_sleep = 0x400027b8 );&lt;br /&gt;
 PROVIDE ( ets_external_printf = 0x40002578 );&lt;br /&gt;
 PROVIDE ( ets_get_cpu_frequency = 0x40002f0c );&lt;br /&gt;
 PROVIDE ( ets_getc = 0x40002bcc );&lt;br /&gt;
 PROVIDE ( ets_install_external_printf = 0x40002450 );&lt;br /&gt;
 PROVIDE ( ets_install_putc1 = 0x4000242c );&lt;br /&gt;
 PROVIDE ( ets_install_putc2 = 0x4000248c );&lt;br /&gt;
 PROVIDE ( ets_install_uart_printf = 0x40002438 );&lt;br /&gt;
 PROVIDE ( ets_intr_lock = 0x40000f74 );&lt;br /&gt;
 PROVIDE ( ets_intr_unlock = 0x40000f80 );&lt;br /&gt;
 PROVIDE ( ets_isr_attach = 0x40000f88 );&lt;br /&gt;
 PROVIDE ( ets_isr_mask = 0x40000f98 );&lt;br /&gt;
 PROVIDE ( ets_isr_unmask = 0x40000fa8 );&lt;br /&gt;
 PROVIDE ( ets_memcmp = 0x400018d4 );&lt;br /&gt;
 PROVIDE ( ets_memcpy = 0x400018b4 );&lt;br /&gt;
 PROVIDE ( ets_memmove = 0x400018c4 );&lt;br /&gt;
 PROVIDE ( ets_memset = 0x400018a4 );&lt;br /&gt;
 PROVIDE ( ets_post = 0x40000e24 );&lt;br /&gt;
 PROVIDE ( ets_printf = 0x400024cc );&lt;br /&gt;
 PROVIDE ( ets_putc = 0x40002be8 );&lt;br /&gt;
 PROVIDE ( ets_rtc_int_register = 0x40002a40 );&lt;br /&gt;
 PROVIDE ( ets_run = 0x40000e04 );&lt;br /&gt;
 PROVIDE ( ets_set_idle_cb = 0x40000dc0 );&lt;br /&gt;
 PROVIDE ( ets_set_user_start = 0x40000fbc );&lt;br /&gt;
 PROVIDE ( ets_str2macaddr = 0x40002af8 );&lt;br /&gt;
 PROVIDE ( ets_strcmp = 0x40002aa8 );&lt;br /&gt;
 PROVIDE ( ets_strcpy = 0x40002a88 );&lt;br /&gt;
 PROVIDE ( ets_strlen = 0x40002ac8 );&lt;br /&gt;
 PROVIDE ( ets_strncmp = 0x40002ab8 );&lt;br /&gt;
 PROVIDE ( ets_strncpy = 0x40002a98 );&lt;br /&gt;
 PROVIDE ( ets_strstr = 0x40002ad8 );&lt;br /&gt;
 PROVIDE ( ets_task = 0x40000dd0 );&lt;br /&gt;
 PROVIDE ( ets_timer_arm = 0x40002cc4 );&lt;br /&gt;
 PROVIDE ( ets_timer_disarm = 0x40002d40 );&lt;br /&gt;
 PROVIDE ( ets_timer_done = 0x40002d80 );&lt;br /&gt;
 PROVIDE ( ets_timer_handler_isr = 0x40002da8 );&lt;br /&gt;
 PROVIDE ( ets_timer_init = 0x40002e68 );&lt;br /&gt;
 PROVIDE ( ets_timer_setfn = 0x40002c48 );&lt;br /&gt;
 PROVIDE ( ets_uart_printf = 0x40002544 );&lt;br /&gt;
 PROVIDE ( ets_update_cpu_frequency = 0x40002f04 );&lt;br /&gt;
 PROVIDE ( ets_vprintf = 0x40001f00 );&lt;br /&gt;
 PROVIDE ( ets_wdt_disable = 0x400030f0 );&lt;br /&gt;
 PROVIDE ( ets_wdt_enable = 0x40002fa0 );&lt;br /&gt;
 PROVIDE ( ets_wdt_get_mode = 0x40002f34 );&lt;br /&gt;
 PROVIDE ( ets_wdt_init = 0x40003170 );&lt;br /&gt;
 PROVIDE ( ets_wdt_restore = 0x40003158 );&lt;br /&gt;
 PROVIDE ( ets_write_char = 0x40001da0 );&lt;br /&gt;
 PROVIDE ( get_first_seg = 0x4000091c );&lt;br /&gt;
 PROVIDE ( gpio_init = 0x40004c50 );&lt;br /&gt;
 PROVIDE ( gpio_input_get = 0x40004cf0 );&lt;br /&gt;
 PROVIDE ( gpio_intr_ack = 0x40004dcc );&lt;br /&gt;
 PROVIDE ( gpio_intr_handler_register = 0x40004e28 );&lt;br /&gt;
 PROVIDE ( gpio_intr_pending = 0x40004d88 );&lt;br /&gt;
 PROVIDE ( gpio_intr_test = 0x40004efc );&lt;br /&gt;
 PROVIDE ( gpio_output_set = 0x40004cd0 );&lt;br /&gt;
 PROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );&lt;br /&gt;
 PROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );&lt;br /&gt;
 PROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );&lt;br /&gt;
 PROVIDE ( gpio_register_get = 0x40004d5c );&lt;br /&gt;
 PROVIDE ( gpio_register_set = 0x40004d04 );&lt;br /&gt;
 PROVIDE ( hmac_md5 = 0x4000a2cc );&lt;br /&gt;
 PROVIDE ( hmac_md5_vector = 0x4000a160 );&lt;br /&gt;
 PROVIDE ( hmac_sha1 = 0x4000ba28 );&lt;br /&gt;
 PROVIDE ( hmac_sha1_vector = 0x4000b8b4 );&lt;br /&gt;
 PROVIDE ( lldesc_build_chain = 0x40004f40 );&lt;br /&gt;
 PROVIDE ( lldesc_num2link = 0x40005050 );&lt;br /&gt;
 PROVIDE ( lldesc_set_owner = 0x4000507c );&lt;br /&gt;
 PROVIDE ( main = 0x40000fec );&lt;br /&gt;
 PROVIDE ( md5_vector = 0x400097ac );&lt;br /&gt;
 PROVIDE ( mem_calloc = 0x40001c2c );&lt;br /&gt;
 PROVIDE ( mem_free = 0x400019e0 );&lt;br /&gt;
 PROVIDE ( mem_init = 0x40001998 );&lt;br /&gt;
 PROVIDE ( mem_malloc = 0x40001b40 );&lt;br /&gt;
 PROVIDE ( mem_realloc = 0x40001c6c );&lt;br /&gt;
 PROVIDE ( mem_trim = 0x40001a14 );&lt;br /&gt;
 PROVIDE ( mem_zalloc = 0x40001c58 );&lt;br /&gt;
 PROVIDE ( memcmp = 0x4000dea8 );&lt;br /&gt;
 PROVIDE ( memcpy = 0x4000df48 );&lt;br /&gt;
 PROVIDE ( memmove = 0x4000e04c );&lt;br /&gt;
 PROVIDE ( memset = 0x4000e190 );&lt;br /&gt;
 PROVIDE ( multofup = 0x400031c0 );&lt;br /&gt;
 PROVIDE ( pbkdf2_sha1 = 0x4000b840 );&lt;br /&gt;
 PROVIDE ( phy_get_romfuncs = 0x40006b08 );&lt;br /&gt;
 PROVIDE ( rand = 0x40000600 );&lt;br /&gt;
 PROVIDE ( rc4_skip = 0x4000dd68 );&lt;br /&gt;
 PROVIDE ( recv_packet = 0x40003d08 );&lt;br /&gt;
 PROVIDE ( remove_head_space = 0x40000a04 );&lt;br /&gt;
 PROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );&lt;br /&gt;
 PROVIDE ( rijndaelKeySetupEnc = 0x40009300 );&lt;br /&gt;
 PROVIDE ( rom_abs_temp = 0x400060c0 );&lt;br /&gt;
 PROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );&lt;br /&gt;
 PROVIDE ( rom_cal_tos_v50 = 0x40007a28 );&lt;br /&gt;
 PROVIDE ( rom_chip_50_set_channel = 0x40006f84 );&lt;br /&gt;
 PROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );&lt;br /&gt;
 PROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );&lt;br /&gt;
 PROVIDE ( rom_chip_v5_rx_init = 0x4000711c );&lt;br /&gt;
 PROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );&lt;br /&gt;
 PROVIDE ( rom_chip_v5_tx_init = 0x4000718c );&lt;br /&gt;
 PROVIDE ( rom_dc_iq_est = 0x4000615c );&lt;br /&gt;
 PROVIDE ( rom_en_pwdet = 0x400061b8 );&lt;br /&gt;
 PROVIDE ( rom_get_bb_atten = 0x40006238 );&lt;br /&gt;
 PROVIDE ( rom_get_corr_power = 0x40006260 );&lt;br /&gt;
 PROVIDE ( rom_get_fm_sar_dout = 0x400062dc );&lt;br /&gt;
 PROVIDE ( rom_get_noisefloor = 0x40006394 );&lt;br /&gt;
 PROVIDE ( rom_get_power_db = 0x400063b0 );&lt;br /&gt;
 PROVIDE ( rom_i2c_readReg = 0x40007268 );&lt;br /&gt;
 PROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );&lt;br /&gt;
 PROVIDE ( rom_i2c_writeReg = 0x400072d8 );&lt;br /&gt;
 PROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );&lt;br /&gt;
 PROVIDE ( rom_iq_est_disable = 0x40006400 );&lt;br /&gt;
 PROVIDE ( rom_iq_est_enable = 0x40006430 );&lt;br /&gt;
 PROVIDE ( rom_linear_to_db = 0x40006484 );&lt;br /&gt;
 PROVIDE ( rom_mhz2ieee = 0x400065a4 );&lt;br /&gt;
 PROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );&lt;br /&gt;
 PROVIDE ( rom_pbus_debugmode = 0x4000737c );&lt;br /&gt;
 PROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );&lt;br /&gt;
 PROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );&lt;br /&gt;
 PROVIDE ( rom_pbus_force_test = 0x4000747c );&lt;br /&gt;
 PROVIDE ( rom_pbus_rd = 0x400074d8 );&lt;br /&gt;
 PROVIDE ( rom_pbus_set_rxgain = 0x4000754c );&lt;br /&gt;
 PROVIDE ( rom_pbus_set_txgain = 0x40007610 );&lt;br /&gt;
 PROVIDE ( rom_pbus_workmode = 0x40007648 );&lt;br /&gt;
 PROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );&lt;br /&gt;
 PROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );&lt;br /&gt;
 PROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );&lt;br /&gt;
 PROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );&lt;br /&gt;
 PROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );&lt;br /&gt;
 PROVIDE ( rom_phy_reset_req = 0x40007804 );&lt;br /&gt;
 PROVIDE ( rom_restart_cal = 0x4000781c );&lt;br /&gt;
 PROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );&lt;br /&gt;
 PROVIDE ( rom_rfcal_rxiq = 0x4000804c );&lt;br /&gt;
 PROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );&lt;br /&gt;
 PROVIDE ( rom_rfcal_txcap = 0x40008388 );&lt;br /&gt;
 PROVIDE ( rom_rfcal_txiq = 0x40008610 );&lt;br /&gt;
 PROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );&lt;br /&gt;
 PROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );&lt;br /&gt;
 PROVIDE ( rom_rfpll_reset = 0x40007868 );&lt;br /&gt;
 PROVIDE ( rom_rfpll_set_freq = 0x40007968 );&lt;br /&gt;
 PROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );&lt;br /&gt;
 PROVIDE ( rom_rxiq_get_mis = 0x40006628 );&lt;br /&gt;
 PROVIDE ( rom_sar_init = 0x40006738 );&lt;br /&gt;
 PROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );&lt;br /&gt;
 PROVIDE ( rom_set_channel_freq = 0x40006c50 );&lt;br /&gt;
 PROVIDE ( rom_set_loopback_gain = 0x400067c8 );&lt;br /&gt;
 PROVIDE ( rom_set_noise_floor = 0x40006830 );&lt;br /&gt;
 PROVIDE ( rom_set_rxclk_en = 0x40006550 );&lt;br /&gt;
 PROVIDE ( rom_set_txbb_atten = 0x40008c6c );&lt;br /&gt;
 PROVIDE ( rom_set_txclk_en = 0x4000650c );&lt;br /&gt;
 PROVIDE ( rom_set_txiq_cal = 0x40008d34 );&lt;br /&gt;
 PROVIDE ( rom_start_noisefloor = 0x40006874 );&lt;br /&gt;
 PROVIDE ( rom_start_tx_tone = 0x400068b4 );&lt;br /&gt;
 PROVIDE ( rom_stop_tx_tone = 0x4000698c );&lt;br /&gt;
 PROVIDE ( rom_tx_mac_disable = 0x40006a98 );&lt;br /&gt;
 PROVIDE ( rom_tx_mac_enable = 0x40006ad4 );&lt;br /&gt;
 PROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );&lt;br /&gt;
 PROVIDE ( rom_write_rfpll_sdm = 0x400078dc );&lt;br /&gt;
 PROVIDE ( roundup2 = 0x400031b4 );&lt;br /&gt;
 PROVIDE ( rtc_enter_sleep = 0x40002870 );&lt;br /&gt;
 PROVIDE ( rtc_get_reset_reason = 0x400025e0 );&lt;br /&gt;
 PROVIDE ( rtc_intr_handler = 0x400029ec );&lt;br /&gt;
 PROVIDE ( rtc_set_sleep_mode = 0x40002668 );&lt;br /&gt;
 PROVIDE ( save_rxbcn_mactime = 0x400027a4 );&lt;br /&gt;
 PROVIDE ( save_tsf_us = 0x400027ac );&lt;br /&gt;
 PROVIDE ( send_packet = 0x40003c80 );&lt;br /&gt;
 PROVIDE ( sha1_prf = 0x4000ba48 );&lt;br /&gt;
 PROVIDE ( sha1_vector = 0x4000a2ec );&lt;br /&gt;
 PROVIDE ( sip_alloc_to_host_evt = 0x40005180 );&lt;br /&gt;
 PROVIDE ( sip_get_ptr = 0x400058a8 );&lt;br /&gt;
 PROVIDE ( sip_get_state = 0x40005668 );&lt;br /&gt;
 PROVIDE ( sip_init_attach = 0x4000567c );&lt;br /&gt;
 PROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );&lt;br /&gt;
 PROVIDE ( sip_install_rx_data_cb = 0x4000545c );&lt;br /&gt;
 PROVIDE ( sip_post = 0x400050fc );&lt;br /&gt;
 PROVIDE ( sip_post_init = 0x400056c4 );&lt;br /&gt;
 PROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );&lt;br /&gt;
 PROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );&lt;br /&gt;
 PROVIDE ( sip_send = 0x40005808 );&lt;br /&gt;
 PROVIDE ( sip_to_host_chain_append = 0x40005864 );&lt;br /&gt;
 PROVIDE ( sip_to_host_evt_send_done = 0x40005234 );&lt;br /&gt;
 PROVIDE ( slc_add_credits = 0x400060ac );&lt;br /&gt;
 PROVIDE ( slc_enable = 0x40005d90 );&lt;br /&gt;
 PROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );&lt;br /&gt;
 PROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );&lt;br /&gt;
 PROVIDE ( slc_init_attach = 0x40005c50 );&lt;br /&gt;
 PROVIDE ( slc_init_credit = 0x4000608c );&lt;br /&gt;
 PROVIDE ( slc_pause_from_host = 0x40006014 );&lt;br /&gt;
 PROVIDE ( slc_reattach = 0x40005c1c );&lt;br /&gt;
 PROVIDE ( slc_resume_from_host = 0x4000603c );&lt;br /&gt;
 PROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );&lt;br /&gt;
 PROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );&lt;br /&gt;
 PROVIDE ( slc_send_to_host_chain = 0x40005de4 );&lt;br /&gt;
 PROVIDE ( slc_set_host_io_max_window = 0x40006068 );&lt;br /&gt;
 PROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );&lt;br /&gt;
 PROVIDE ( software_reset = 0x4000264c );&lt;br /&gt;
 PROVIDE ( spi_flash_attach = 0x40004644 );&lt;br /&gt;
 PROVIDE ( srand = 0x400005f0 );&lt;br /&gt;
 PROVIDE ( strcmp = 0x4000bdc8 );&lt;br /&gt;
 PROVIDE ( strcpy = 0x4000bec8 );&lt;br /&gt;
 PROVIDE ( strlen = 0x4000bf4c );&lt;br /&gt;
 PROVIDE ( strncmp = 0x4000bfa8 );&lt;br /&gt;
 PROVIDE ( strncpy = 0x4000c0a0 );&lt;br /&gt;
 PROVIDE ( strstr = 0x4000e1e0 );&lt;br /&gt;
 PROVIDE ( timer_insert = 0x40002c64 );&lt;br /&gt;
 PROVIDE ( uartAttach = 0x4000383c );&lt;br /&gt;
 PROVIDE ( uart_baudrate_detect = 0x40003924 );&lt;br /&gt;
 PROVIDE ( uart_buff_switch = 0x400038a4 );&lt;br /&gt;
 PROVIDE ( uart_div_modify = 0x400039d8 );&lt;br /&gt;
 PROVIDE ( uart_rx_intr_handler = 0x40003bbc );&lt;br /&gt;
 PROVIDE ( uart_rx_one_char = 0x40003b8c );&lt;br /&gt;
 PROVIDE ( uart_rx_one_char_block = 0x40003b64 );&lt;br /&gt;
 PROVIDE ( uart_rx_readbuff = 0x40003ec8 );&lt;br /&gt;
 PROVIDE ( uart_tx_one_char = 0x40003b30 );&lt;br /&gt;
 PROVIDE ( wepkey_128 = 0x4000bc40 );&lt;br /&gt;
 PROVIDE ( wepkey_64 = 0x4000bb3c );&lt;br /&gt;
 PROVIDE ( xthal_bcopy = 0x40000688 );&lt;br /&gt;
 PROVIDE ( xthal_copy123 = 0x4000074c );&lt;br /&gt;
 PROVIDE ( xthal_get_ccompare = 0x4000dd4c );&lt;br /&gt;
 PROVIDE ( xthal_get_ccount = 0x4000dd38 );&lt;br /&gt;
 PROVIDE ( xthal_get_interrupt = 0x4000dd58 );&lt;br /&gt;
 PROVIDE ( xthal_get_intread = 0x4000dd58 );&lt;br /&gt;
 PROVIDE ( xthal_memcpy = 0x400006c4 );&lt;br /&gt;
 PROVIDE ( xthal_set_ccompare = 0x4000dd40 );&lt;br /&gt;
 PROVIDE ( xthal_set_intclear = 0x4000dd60 );&lt;br /&gt;
 PROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );&lt;br /&gt;
 PROVIDE ( xthal_window_spill = 0x4000e324 );&lt;br /&gt;
 PROVIDE ( xthal_window_spill_nw = 0x4000e320 );&lt;br /&gt;
 &lt;br /&gt;
 PROVIDE ( Te0 = 0x3fffccf0 );&lt;br /&gt;
 PROVIDE ( Td0 = 0x3fffd100 );&lt;br /&gt;
 PROVIDE ( Td4s = 0x3fffd500);&lt;br /&gt;
 PROVIDE ( rcons = 0x3fffd0f0);&lt;br /&gt;
 PROVIDE ( UartDev = 0x3fffde10 );&lt;br /&gt;
 PROVIDE ( flashchip = 0x3fffc714);&lt;/div&gt;</summary>
		<author><name>Eric</name></author>
	</entry>
</feed>